The control register contains the enable interrupt bit and reset for the receive and transmit data FIFO. This is write only register. Issuing a read request to the control register generates the read acknowledgment with zero data. The register bit assignment is shown in
Table: Monitor Control Register (MON_CTRL)
and described in
Table: Monitor Control Register Bit Definitions
. The register is only implemented if C_INTERFACE is set to 0.
Table 2-58:
Monitor Control Register (MON_CTRL)
Reserved
|
MON_CTRL
|
31
|
5
|
4
|
0
|
Table 2-59:
Monitor Control Register Bit Definitions
Bits
|
Name
|
Access
|
Reset
Value
|
Description
|
31-5
|
Reserved
|
N/A
|
0
|
Reserved
|
4
|
Interrupt Enabled
|
W
|
0
|
Enable interrupt for the MDM JTAG Monitor
0 = Disable interrupt signal
1 = Enable interrupt signal
|
3-2
|
Reserved
|
N/A
|
0
|
Reserved
|
1
|
Reset RX FIFO
|
W
|
1
|
Reset/clear the receive FIFO
Writing a 1 to this bit position clears the receive FIFO
0 = Do nothing
1 = Clear the receive FIFO
|
0
|
Reset TX FIFO
|
W
|
1
|
Reset/clear the transmit FIFO
Writing a 1 to this bit position clears the transmit FIFO
0 = Do nothing
1 = Clear the transmit FIFO
|