Monitor Transmit Register (MON_TRANSMIT) - 1.0 English

MicroBlaze Triple Modular Redundancy (TMR) Subsystem (PG268)

Document ID
PG268
Release Date
2022-04-28
Version
1.0 English

This 32-entry-deep FIFO contains data transmitted to the SEM monitor. The FIFO bit definitions are shown in Table: Monitor Transmit Register (MON_TRANSMIT) . Data to be transmitted is written into this register. When a write request is issued while the FIFO is full, a bus error (SLVERR) is generated and the data is not written into the FIFO. This is a write-only location. Issuing a read request to the transmit data FIFO generates the read acknowledgment with zero data. Table:  Monitor Transmit FIFO Register Bit Definitions shows the location for data on the AXI interface. The register is only implemented if C_INTERFACE is set to 0.

Table 2-54: Monitor Transmit Register (MON_TRANSMIT)

Reserved

MON_TX

31

8

7

0

Table 2-55: Monitor Transmit FIFO Register Bit Definitions

Bits

Name

Access

Reset
Value

Description

31:8

-

R

0

Reserved

7:0

MON_TX

R

0

Monitor Transmit Data