The SEM sticky status register saves the status signals from the TMR SEM core. This is a read/write register. If a write request is issued to the SEM sticky status register bits set to one in the written data are cleared. The register bit assignment is shown in
Table: SEM Sticky Status Register (SEMSSR)
and described in
Table: SEM Sticky Status Register Bit Definitions
. The register is only implemented if C_SEM_INTERFACE is set to 1.
Table 2-36:
SEM Sticky Status Register (SEMSSR)
Reserved
|
DS
|
DO
|
ESS
|
UNC
|
INJ
|
CLA
|
CORR
|
OBS
|
INI
|
HB
|
HBWE
|
31
|
11
|
10
|
9
|
8
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
Table 2-37:
SEM Sticky Status Register Bit Definitions
Bits
|
Name
|
Access
|
Reset
Value
|
Description
|
31-11
|
Reserved
|
N/A
|
0
|
Reserved
|
10
|
Diagnostic Scan
|
R
|
0
|
Set to 1 by the SEM Diagnostic Scan input.
Cleared by writing 1 to the bit.
|
9
|
Detect Only
|
R
|
0
|
Set to 1 by the SEM Detect Only input.
Cleared by writing 1 to the bit.
|
8
|
Essential
|
R
|
0
|
Set to 1 by the SEM Essential input.
Cleared by writing 1 to the bit.
|
7
|
Uncorrectable
|
R
|
0
|
Set to 1 by the SEM Uncorrectable input.
Cleared by writing 1 to the bit.
|
6
|
Injection
|
R
|
0
|
Set to 1 by the SEM Injection input.
Cleared by writing 1 to the bit.
|
5
|
Classification
|
R
|
0
|
Set to 1 by the SEM Classification input.
Cleared by writing 1 to the bit.
|
4
|
Correction
|
R
|
0
|
Set to 1 by the SEM Correction input.
Cleared by writing 1 to the bit.
|
3
|
Observation
|
R
|
0
|
Set to 1 by the SEM Observation input.
Cleared by writing 1 to the bit.
|
2
|
Initialization
|
R
|
0
|
Set to 1 by the SEM Initialization input.
Cleared by writing 1 to the bit.
|
1
|
Heartbeat
|
R
|
0
|
Set to 1 by the SEM Heartbeat input signal.
Cleared by writing 1 to the bit.
|
0
|
Heartbeat Watchdog Expired
|
R
|
0
|
The SEM heartbeat watchdog has expired since writing this register to clear the status:
0 = The watchdog has not expired.
1 = The watchdog has expired.
Cleared by writing 1 to the bit.
|