The TMR Comparator and TMR Voter adhere to the AMBA ® AXI4, ACE and AXI4-Lite Interface standard (see Arm ® AMBA AXI and ACE Protocol Specification Arm IHI 0022E [Ref 2] ).
The TMR Comparator and TMR Voter adhere to the AMBA AXI4-Stream Interface standard (see Arm AMBA AXI4-Stream Protocol Specification, Version 1.0 [Ref 3] ).
The I/O bus interface provided by the I/O Module core handled by the TMR Comparator and TMR Voter is fully compatible with the Xilinx Dynamic Reconfiguration Port (DRP). For a detailed description of the DRP, see the 7 Series FPGAs Configuration User Guide (UG470) [Ref 4] .
The TMR SEM adheres to the AMBA AXI4-Lite Interface (see Arm AMBA AXI and ACE Protocol Specification Arm IHI 0022E [Ref 2] ).