AXI4-Stream Related Ports for RF-ADCs - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)
Document ID
PG269
Release Date
2022-10-21
Version
2.6 English
Table 1. AXI4-Stream Related Ports for RF-ADCs
Port Name 1 I/O Clock Description
mX_axis_aclk In N/A Clock input for RF-ADC data output
mX_axis_aresetn In N/A Synchronous reset for the mX_axis_aclk domain. This should be held low until mX_axis_aclk is stable. The reset can be asserted asynchronously but its deassertion must be synchronous to sX_axis_aclk.
mXY_axis_tdata[M:0] Out mX_axis_aclk AXI4-Stream data output
mXY_axis_tvalid Out mX_axis_aclk AXI4-Stream valid
mXY_axis_tready In mX_axis_aclk AXI4-Stream ready. Not used in IP core.
Quad RF-ADC Tile vinXZ_p In N/A Analog input
vinXZ_n In N/A Analog input
Dual RF-ADC Tile vinX_ZZ_p In N/A Analog input
vinX_ZZ_n In N/A Analog input
  1. X refers to the location of the tile in the converter column. Y refers to the location of the DDC block in the tile (0 to 3). In Quad RF-ADC tile devices, Z refers to the location of the RF-ADC in the tile (0 to 3). In Dual RF-ADC tile devices, ZZ is either 01 (the lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile). M is the number of samples per AXI4-Stream word * 16 for converter XY.