AXI4-Stream Related Ports for RF-DACs - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2023-10-18
Version
2.6 English
Table 1. AXI4-Stream Related Ports for RF-DACs
Port Name 1 I/O Clock Description
sX_axis_aclk In N/A Clock input for RF-DAC data input
sX_axis_aresetn In N/A Active-Low synchronous reset for the sX_axis_aclk domain. This should be held low until sX_axis_aclk is stable. The reset can be asserted asynchronously but deassertion must be synchronous to sX_axis_aclk.

This resets the RF-DAC data path and input FIFO.

sXY_axis_tdata[M:0] In sX_axis_aclk AXI4-Stream data input
sXY_axis_tvalid In sX_axis_aclk AXI4-Stream valid. This port is present to ensure AXI4-Stream compatibility. It is not used in the IP core.
sXY_axis_tready Out sX_axis_aclk AXI4-Stream ready
voutXZ_p Out N/A Analog output
voutXZ_n Out N/A Analog output
  1. X refers to the location of the tile in the converter column. Y refers to the location of the DUC block in the tile (0 to 3). Z refers to the location of the RF-DAC in the tile (0 to 3). M is the number of samples per AXI4-Stream word * 16 for converter XY.