| sX_axis_aclk |
In |
N/A |
Clock input for RF-DAC data input
|
| sX_axis_aresetn |
In |
N/A |
Synchronous reset for the sX_axis_aclk domain. This should be held low
until sX_axis_aclk is stable. The reset can be asserted asynchronously but deassertion must
be synchronous to sX_axis_aclk. |
| sXY_axis_tdata[M:0] |
In |
sX_axis_aclk |
AXI4-Stream data input |
| sXY_axis_tvalid |
In |
sX_axis_aclk |
AXI4-Stream valid. This port is
present to ensure AXI4-Stream compatibility. It is not used in the IP
core. |
| sXY_axis_tready |
Out |
sX_axis_aclk |
AXI4-Stream ready |
| voutXZ_p |
Out |
N/A |
Analog output |
| voutXZ_n |
Out |
N/A |
Analog output |
- X refers to the location of the tile in the
converter column. Y refers to the location of the DUC block in the tile (0 to 3). Z refers
to the location of the RF-DAC in the tile (0 to 3). M is
the number of samples per AXI4-Stream word * 16 for
converter XY.
|