Bitstream Reconfiguration - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English
Note: The RFSoC devices are reliable as long as the Recommended Operating conditions specified in the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) are not violated. In case the power distribution network can exhibit voltage overshoot exceeding the maximum operating condition during bitstream reconfiguration, then the below procedure is recommended to prevent any impact on the lifetime reliability of the device.

To load a new bitstream or reload the current bitstream into the Zynq® UltraScale+™ RFSoC when there are one or more tiles in operation then the following steps must be followed to ensure safe operation. Failing to follow these steps during a reconfiguration event can potentially impact lifetime reliability of the part.

  1. Mute the analog front end to avoid TX and RX signaling.
  2. Individually shut down all RF-ADC and RF-DAC tiles used using the XRFDC_Shutdown API command or the Power-Down Tile registers.
  3. Load the new bitstream or reload the existing bitstream.
  4. After configuration, the tiles will start up in the correct sequence by the power-up state machine in the IP.