Clock Ports Common to RF-ADC Tile - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2022-10-21
Version
2.6 English
Table 1. Clock Ports Common to RF-ADC Tile
Port Name 1 I/O Clock Description
adcX_clk_p In N/A RF-ADC on-chip PLL reference clock or sampling clock input
adcX_clk_n In N/A RF-ADC on-chip PLL reference clock or sampling clock input
clk_adcX Out N/A Output clock to user logic
  1. X refers to the location of the tile in the converter column.