Compensation Using PL Gain - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

For wider dynamic range digital gain adjustment, the FPGA PL can be used. Similarly to the QMC Gain method, the latency through the VGA, RF-ADC and datapath should be used to delay the application of the gain change in the PL. After the PL gain change, the thresholds can be cleared by a call to the XRFdc_ThresholdStickyClear API function, or by issuing an adcXY_pl_event after the event source has been set by a call to the XRFdc_SetQMCSettings API function.