Detailed Description - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

In any system with multiple independent converters and clocking structures, there are several potential sources of latency uncertainty, such as the clock divider phase, NCO phase, FIFO latencies, clock skew, and data skew. Discrete converters have standardized the use of the JESD204B SYSREF scheme for synchronization, and as a result the Zynq® UltraScale+™ RFSoCs have implemented a complementary, simplified scheme using SYSREF.

Figure 1. Zynq® UltraScale+™ RFSoC Multi-Tile Synchronization Example

The integration of the converters in the Zynq® UltraScale+™ RFSoCs results in the elimination of the serial transceiver links for data communication. However, to provide a flexible clocking and number of data words for the PL design, each RF-ADC and RF-DAC incorporates independent gearbox FIFOs. These FIFOs allow data to be transferred between the PL clock domain to the converter sample clock domain, but this results in a non-deterministic latency that must also be measured and corrected for by using SYSREF.

The Zynq® UltraScale+™ RFSoC RF Data Converter and RFdc driver API solution provide an easy to use and integrated way to synchronize each of the tiles in a given device. The previous figure shows an example system with multiple tiles which are to be synchronized. The following applies to the previous figure:

  • Two RF-DAC tiles are shown for the purposes of illustration, but the method applies equally to any number of RF-ADC or RF-DAC tiles.
  • A single analog SYSREF input per device is distributed internally to all RF-ADCs and RF-DACs.
  • There is an internal analog SYSREF delay adjust per tile, to ease PCB requirements by allowing SYSREF setup/hold time to be optimized on-chip.
  • There is an analog clock input per tile; these are shown as DAC0_CLK and DAC1_CLK.
  • The common clock for the PL user design and tiles is shown as PL Clock (PL_clock).
  • The SYSREF for the PL is shown as PL SYSREF (PL_SysRef). There is a separate PL SYSREF for RF-ADCs (user_sysref_adc) and RF-DACs (user_sysref_dac) if both are in the synchronization group.
  • The synchronization state machine is contained within the core, which, with the RFdc driver API, implements the synchronization solution.
  • For RF-DAC multi-tile synchronization (MTS), the RF-DAC tile master is always used as the reference tile for all other RF-DAC tiles to synchronize to. As a result, RF-DAC tile 0 must be an active tile and RF-DAC tile 0 channel 0 must be used in the application of MTS for the RF-DAC.
  • Similarly, the RF-ADC tile master is always used as the reference tile for the synchronization of all other RF-ADC tiles. As a result, RF-ADC tile 0 must be an active tile and RF-ADC tile 0 channel 0 must be used in the application of MTS for the RF-ADC.
  • If it is required to disable a tile that is present in the SYSREF chain it should be powered down to state 3 in the power-on sequence in Gen 1 and Gen 2 devices and to state 6 in Gen 3 devices and DFE devices. This ensures that the SYSREF is still propagated along the chain.
  • Package flight time skew for each converter should be taken into account and adjusted for during PCB design.