Deterministic Multi-Tile Synchronization API Use - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
Release Date
2.6 English

The multi-tile API use outlined in the previous section guarantees alignment between tiles in each group. However, the total latency through the tiles can vary by a number of words related to the FIFO read-clock period divided by the number of read-words. For applications where the total latency must be constant, the Target_Latency setting in the API can be enabled. This setting adjusts all delays less than the target to the target value; any measured values greater than the target results in an error message, while the MTS still align all tiles by ignoring the Target_Latency. To prevent this error, the Target_Latency value must first be determined for the user FIFO and tile configuration by running XRFdc_MultiConverter_Sync with the target set to -1. The returned latency value (plus some margin) must be set as the target value for future runs.

The margin value to be applied is specified in terms of sample clocks. For the RF-ADC tiles, this value must be a multiple of the number of FIFO read-words times the decimation factor, and for RF-DAC tiles this value can be a constant of 16. An example of setting the target latency is as follows:

XRFdc_MultiConverter_Init (&DAC_Sync_Config, 0, 0, 0); // Initialize DAC MTS Settings
DAC_Sync_Config.Tiles = 0x3;               // Tiles to sync bit-mask: DAC tiles 0 and 1
DAC_Sync_Config.Target_Latency = 296;      // Target latency - measured value (280 + 16 margin)