Dual RF-ADC I/Q Input to I/Q Output - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2022-10-21
Version
2.6 English

For I/Q input to I/Q output, the RF-ADCs are paired.

Figure 1. Dual RF-ADC I/Q Input to I/Q Output
Figure 2. Dual RF-ADC I/Q Input to I/Q Output IP Core Configuration

The following figure shows a Dual RF-ADC with I/Q input to I/Q output, 1x decimation, the mixer enabled, and running at a 500 MHz AXI4-Stream clock.

Figure 3. Dual RF-ADC I/Q Input to I/Q Output Timing
Important: I/Q input to I/Q output configurations are not available on devices with one RF-ADC per tile.