Figure 1. Dual RF-ADC Real Input to Real
Output
Figure 2. Dual RF-ADC Real Input to Real
Output IP Configuration
The following figure shows a Dual RF-ADC with real data input to real data output, 1x decimation, the mixer bypassed and running at a 500 MHz AXI4-Stream clock.
Figure 3. Dual RF-ADC Real Input to Real
Output Data Timing