IP Facts - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
Release Date
2.6 English
LogiCORE IP Facts Table
Core Specifics
Supported Device Family 1 Zynq® UltraScale+™ RFSoC
Supported User Interfaces AXI4-Stream, AXI4-Lite Control/Status
Resources Performance and Resource Use web page
Provided with Core
Design Files RTL
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx Design Constraints (XDC)
Simulation Model Verilog
Supported S/W Driver 2 Standalone and Linux
Tested Design Flows 3
Design Entry Vivado® IP integrator
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Release Notes and Known Issues Master Answer Record: 69907
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. Standalone driver details can be found in the software development kit <Install Directory>/Vitis/<Release>/data/embeddedsw/doc/Xilinx_drivers.htm.

    Bare-metal/Linux documentation is available in Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver.

  3. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.