|
Core Specifics |
| Supported Device Family
1
|
Zynq®
UltraScale+™ RFSoC
|
| Supported User Interfaces |
AXI4-Stream,
AXI4-Lite Control/Status |
| Resources |
Performance and Resource Use web
page
|
| Provided with Core
|
| Design Files |
RTL |
| Example Design |
Verilog |
| Test Bench |
Verilog |
| Constraints File |
Xilinx Design Constraints
(XDC) |
| Simulation Model |
Verilog |
| Supported S/W Driver
2
|
Standalone and Linux |
| Tested Design Flows
3
|
| Design Entry |
Vivado®
IP
integrator |
| Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 69907
|
| All Vivado IP Change
Logs |
Master Vivado IP Change Logs:
72775
|
|
Xilinx
Support web page
|
- For a complete list of supported devices, see the
Vivado®
IP catalog.
- Standalone driver details can be found in the
software development kit <Install
Directory>/Vitis/<Release>/data/embeddedsw/doc/Xilinx_drivers.htm.
Bare-metal/Linux documentation is available in Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver.
- For the supported versions of third-party tools, see
the Xilinx Design Tools: Release Notes
Guide.
|