Interrupt Setup and Handling Example - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2023-10-18
Version
2.6 English

The following code shows an interrupt setup and handling example.

//
// Handler
//
// User-Defined interrupt status handler

void RFdcHandler (void *CallBackRef, u32 Type, int Tile, u32 Block, u32 Event) {
// Check the type of interrupt event

  if (Type == XRFDC_DAC_TILE) {
     xil_printf("\nInterrupt occurred for ADC%d,%d :", Tile_Id, Block_Id);
     if(Event & (XRFDC_IXR_FIFOUSRDAT_OF_MASK | XRFDC_IXR_FIFOUSRDAT_UF_MASK)) {
        xil_printf("FIFO Actual Overflow\r\n");
     }
     if(Event & (XRFDC_IXR_FIFOMRGNIND_OF_MASK | XRFDC_IXR_FIFOMRGNIND_UF_MASK)){
        xil_printf("FIFO Marginal Overflow\r\n");
     }
     if(Event & XRFDC_DAC_IXR_INTP_STG_MASK)) {
        xil_printf("Interpolation Stages Overflow\r\n");
     }
     // ... Other handling code ...
  } else {        
       xil_printf("\nInterrupt occurred for ADC%d,%d :\r\n", Tile_Id, Block_Id);
       // ... ADC handling code ...
  }
}

//
// Setup
//
// Register the user-defined interrupt handler

XRFdc_SetStatusHandler(ptr, ptr, (XRFdc_StatusHandler) RFdcHandler);
//
// Setup for RF-DAC tile 0, block 0 - FIFO Interrupt
//
XRFdc_IntrEnable(ptr, XRFDC_DAC_TILE, 0, 0, XRFDC_IXR_FIFOUSRDAT_MASK);
//
// Test
//
// Force a FIFO interrupt by setting the FIFO write words to a different value from the design requirements. 
// Note: Assumes a value of 1 is invalid for this design.
XRFdc_SetFabRdVldWords(ptr, 0, 0, 1); 

This example shows the RFdc driver-specific interrupt handling and the forcing of an interrupt by changing the FIFO parameters. The setup and registration of the RF Data Converter irq output with the PS or MicroBlaze™ interrupt controller is not shown. For more details, see the examples provided with the RFdc driver API (see the Zynq UltraScale+ Device Technical Reference Manual (UG1085)).