Main Sequence to Perform Synchronization for AC or DC Coupled Single or Multiple Device - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

The following flowchart shows the main sequence to perform synchronization.

Figure 1. Flowchart of MTS Main Sequence

The following steps reflect the main sequence flowchart in more details and provide API usage examples:

  1. Enable PL SYSREF and analog SYSREF clocks in continuous clock mode.
  2. Wait for clocks to stabilize, typically in the order of microseconds (µs), depending on what clock device is used.
  3. If deterministic latency is not required or unknown, run RF-ADC and/or RF-DAC MTS API functions with target latency and set target latency as -1. An example synchronizing DAC tile 0 and 1 is given below:
    int status_dac;
    XRFdc_MultiConverter_Sync_Config DAC_Sync_Config; // Declare DAC MTS Settings struct       
    XRFdc_MultiConverter_Init (&DAC_Sync_Config, 0, 0, 0);  // Initialize DAC MTS Settings
    DAC_Sync_Config.Tiles = 0x3;   // Tiles to sync bit-mask: DAC tiles 0 and 1
    DAC_Sync_Config.Target_Latency = 296; // Target latency = 280 (measured value) + 16 (margin), set to -1 if unknown
    status_dac=XRFdc_Multiconverter_Sync(RFdcInstPtr,XRFDC_DAC_TILE,&DAC_Sync_Config); // Run Multi-Tile-Sync for the DAC Group
  4. Wait for completion of API return value.
    if (status_dac!=XRFDC_MTS_OK) {Execute error code;} and Report details on synchronization (optional)
    for(i=0; i<4; i++) {
    	if((1<<i)&DAC_Sync_Config.Tiles) {
    		XRFdc_GetInterpolationFactor(RFdcInstPtr, i, 0, &factor);
    		xil_printf(" DAC%d: Latency(T1) =%3d, Adjusted Delay 
    	     (T%d) =%3d\n", i, DAC_Sync_Config.Latency[i], factor, 
    Note: The apparent latency value reported must not be confused with the absolute FIFO or tile data latency; it is a relative latency value of each tile.
  5. Synchronize digital features (mixer settings, NCO phase reset, QMC, and/or coarse delay) depending on use case:
    Use Case 1
    Single device SYSREF with AC- or DC-Coupling.
    Use Case 2
    Multiple devices SYSREF with DC-Coupling.
  6. External PL SYSREF and analog SYSREF clocks can be disabled (optional).