Multi-Tile Mode - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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When multi-tile synchronization is selected the SYSREF is used to update the NCO settings. This ensures that the mixer updates are synchronized across all the converters. Before an NCO update can take place the event source must be set to SYSREF. See Dynamic Update Events (link below) for more information on setting the event source.

Because the SYSREF is used to trigger the NCO update it should be gated to ensure that an edge does not arrive during the update process. If the SYSREF is gated externally the IP core works in the same way as the single converter case. In Gen 3/DFE devices, you have the option to gate the SYSREF internally in the IP by asserting the dac{x}_sysref_gate real-time input. In this case the IP core also works in the same way as the single converter case. The SYSREF should be turned off before the NCO update process is started and re-enabled when the IP has deasserted the busy signal.

If neither of the SYSREF gating methods described above is implemented, the IP core can gate the SYSREF signal internally by writing to registers in RF-DAC tile 0. In this case the process for updating the NCO settings is shown below.

Figure 1. Multi-Tile NCO Update
  • First, set the required NCO frequency, phase, and phase reset values on the Real-Time NCO signal interface ports for all NCO channels that are to be updated. At the same time the update enable ports (dac0_update_en, dac{x}_update_en) should be set to indicate which register values are to be updated.
  • Drive dac0_sysref_int_gating High to indicate to the IP that it should gate the SYSREF internally.
  • To start the NCO update, send a pulse to the dac0_nco_update_req port.
  • When the IP receives the update request, it first waits for the startup state machine to complete and then carries out the register writes that are required to gate the SYSREF in RF-DAC tile 0. When this is completed it drives Bit 1 of the dac0_nco_update_busy output High.
  • You can then assert the update request inputs for the other converters in the multi-tile synchronization group (dac{x}_update_req) to request their NCO updates through the Real-Time NCO signal interface.
  • When all the update busy outputs for the converter in the multi-tile synchronization group are Low, with the exception of dac0_nco_update_busy[1], the NCO register writes have been completed. The busy outputs can be deasserted asynchronously to each other.
  • You should then send a pulse to the dac0_sysref_int_reenable port to indicate that SYSREF can be restarted. The process is complete when dac0_nco_update_busy[1] goes Low.

The update process waits until the IP state machine has completed the start up process before accessing the requested NCO registers.

The more values that are required to be updated increases the time to write the NCO values into the registers. This is shown for RF-DAC tile 0 as T1 in the preceding figure. In the RF-DAC and Quad RF-ADC cases, writing one register typically takes 29 s_axi_aclk cycles. Each additional register write increases T1 by three s_axi_aclk cycles. In the Dual RF-ADC case, writing one register typically takes 45 s_axi_aclk cycles. Each additional register write increases T1 by 6 s_axi_aclk cycles..

In the preceding figure, T2 indicates the time taken for the process to complete from the start of the initial register updates. This time depends on the SYSREF frequency, the number of register values to be updated, and the number of converters in the tile synchronization group.