Multi-Tile Synchronization Ports - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2023-10-18
Version
2.6 English
Table 1. Multi-Tile Synchronization Ports
Port Name I/O Clock Description 1
sysref_in_p In N/A External analog SYSREF input
sysref_in_n In N/A External analog SYSREF input
user_sysref_adc In m0_axis_aclk RF-ADC SYSREF input from programmable logic (PL)/ user design; synchronous to RF-ADC tile 0 PL clock
user_sysref_dac In s0_axis_aclk RF-DAC SYSREF input from programmable logic (PL)/user design; synchronous to RF-DAC tile 0 PL clock
  1. See the Multi-Tile Synchronization section in the Applications sub-section for more information.