When an outside common-mode event occurs the input buffer is effectively disabled and automatically protected.
The level flag
cm_over_voltage is sent to the PL if an under or over
common-mode signal is detected. Because the RF-ADC is
disabled during this event the data in the digital datapath is gated to 0. The
calibration phase of the power-up process will not commence until the common-mode is
within the safe operating range.
cm_over_voltage signal remains set while the common-mode is
outside the thresholds and automatically deasserts when the common mode returns to the
safe operating range. This is shown in the following figure:
For detailed parameters of over-voltage protection, see the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).