Over Voltage (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2023-10-18
Version
2.6 English

An over-voltage condition is detected within the RF-ADC analog input buffer block, and is communicated using flags. The analog block also protects the inputs when these conditions are detected. This protection is automatic and does not require any configuration or interaction from the digital circuitry. Two types of over-voltage are handled:

Over Amplitude
This is where the buffer output amplitude is too large for the RF-ADC core, it is detected on the single-ended buffer outputs. When an Over Amplitude condition is detected, it is flagged by both the interrupt mechanism, and by asserting the over_voltage real-time output signal.
Outside Common-Mode range
This is where the common-mode at the input is over/under the reliable range. When a common mode under or over voltage condition is detected it is flagged by both the interrupt mechanism, and by asserting the cm_over_voltage or cm_under_voltage real-time output signal.

The following figure shows where the above two input violations are detected:

Figure 1. Positions of OV Detectors