The AXI4-Stream data for all four tile streams is synchronous to a clock from the PL, which has a naming convention of sX_axis_aclk, where X represents the RF-DAC tile number. This clock must be at the frequency specified by the Required AXI4-Stream clock displayed on the IP core configuration screen.
The RF-DAC tile also outputs a clock that can be used by the PL. This output clock is a divided version of the RF-DAC sample clock and therefore is frequency locked to it. This clock has a naming convention of clk_dacX, where X represents the RF-DAC tile number.