To guarantee effective synchronization between tiles, it is important to reliably capture the PL SYSREF input in the device logic. The PL SYSREF and PL clock inputs must be differential signals that obey the clock and banking rules for the device. The PL clock input must be on a dedicated clock pin. The AXI4-Stream clocks for the Zynq® UltraScale+™ RF Data Converter core must be generated from the PL clock input and not from the clock outputs from the core itself. The following figure shows an example PL SYSREF capture circuit where the RF-ADC and RF-DAC are operating at the same AXI4-Stream clock frequency.
report_datasheet command can be used in the
Vivado IDE to calculate the required setup and
hold times for the PL SYSREF input at the device pins. The following figure shows an
example calculation for a -1 speed grade device with a 500 MHz PL clock.
|Reference Clock||Input Port||Setup (ns) to Clk (Edge)||Hold (ns) to Clk (Edge)|
|pl_clk||pl_sysref_n||0.965 (r)||0.285 (r)|
|pl_clk||pl_sysref_p||0.965 (r)||0.285 (r)|
In the example above, the PL SYSREF must be delayed to arrive at least 0.285 ns
after the rising edge of the PL clock to ensure the hold requirement is met. For each
new design, or when the design is changed, the
report_datasheet step should be run to reevaluate the setup and hold
requirements. If the RF-ADC and RF-DAC are operating at different AXI4-Stream clock frequencies, the circuit shown in the following figure
can be used to capture PL SYSREF.
Here, the clock network deskew MMCMs are used to synthesize the frequency of the PL clock to the required rates. The PL clock must be a common multiple or sub-multiple of the RF-ADC and RF-DAC AXI4-Stream clocks if MTS across multiple tiles is required (provided it is related by an integer value (for example, 1/8, 1/4, 1/2, 1x, 2x, 4x, 8x)). In addition, the PL SYSREF frequency must be a common sub-multiple of all the clocks in the system.