QMC Overflow - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2022-10-21
Version
2.6 English

Setting excessive gain, phase or offset correction factors relative to the input signal can cause the datapath to overflow. To aid system debug, the QMC block contains built-in overflow detection and saturation blocks. These blocks generate flags which are connected to the IP interrupt mechanism using the datapath interrupt. The related interrupt flags for the QMC block are:

XRFDC_IXR_QMC_GAIN_PHASE_MASK

XRFDC_IXR_QMC_OFFST_MASK

These interrupts can be enabled per converter channel.

  • The gain correction multiplier range is between 0 and 2.0.
  • The range of the phase correction multiplier is approximately ±26 degrees, or ±0.5 in terms of magnitude.