Quad RF-ADC Real Input to I/Q Output - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2023-10-18
Version
2.6 English
Figure 1. Quad RF-ADC Real Input to I/Q Output
Figure 2. Quad RF-ADC Real Input to I/Q Output IP Core Configuration

The following figure shows a Quad RF-ADC real input data to I/Q output data, 1x decimation, the mixer enabled, and running at a 500 MHz AXI4-Stream clock. Note that each I/Q channel is interleaved on the output data stream.

Figure 3. Quad RF-ADC Real Input to I/Q Output Timing