RF-ADC Analog Supply Power Sequencing (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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There is a recommended power up and down sequence for the RF-ADC supplies for safe operation. The following figure shows the recommended sequence where the ADC_AVCC supply should be powered up after the ADC_AVCCAUX supply is brought up, and powered down before the ADC_AVCCAUX supply is brought down.

There is no specific delay time between supply ramps as long as a sequence is followed/respected.

Figure 1. RF-ADC Analog Supply Power Sequencing

This can be enabled if the implemented power management has Power Good and Enable pins which are common on most regulators. The Power Good indicator of the ADC_AVCCAUX can be used as theEnable control of the ADC_AVCC regulator. Look at the power distribution network on the Xilinx ZCU216 customer board as a reference, or contact your local FAE. Xilinx recommends full switched mode power supply solutions for the data converter analog supplies due to the increased power efficiency over low-dropout (LDO)-based solutions for most applications.