RF-ADC Calibration Mechanism - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

Each of the RF-ADCs in the Zynq UltraScale+ RFSoC is built on multiple sub-RF-ADCs in an interleaving architecture. The nature of the interleaving process requires that an intricate calibration algorithm to be carried out to obtain the best dynamic range performance from the RF-ADC. Each of the RF-ADCs (Dual or Quad variant) in the RFSoC has a built-in calibration process that includes a foreground calibration (FG CAL) step and a background calibration (BG CAL) step. The FG CAL step gets executed during the RF-ADC power-on state machine (startup initialization) only. The BG CAL step is a process that is designed to operate optionally during the RF-ADC run-time. Both of the calibration steps for each RF-ADC is carried out in parallel and independently. The following figure shows the block diagram of one of the RF-ADCs with the internal calibration blocks for each of the N sub-RF-ADCs.

Figure 1. RF-ADC Calibration Block Diagram (Gen 1/Gen 2)
Figure 2. RF-ADC Calibration Block Diagram (Gen 3/DFE)

The calibration sub-system comprises of three major blocks that are designed to estimate and correct the various imperfections and mismatches of the interleaving sub-RF-ADCs.