Decimation filters are required to implement the down-sampling and filtering part of the digital-down conversion (DDC) process. The overall filter response is determined by the number of decimation stages used. The decimation chain consists of three FIR filter stages which can be combined to implement variable decimation rates. When a FIR stage is not used it is automatically powered down. The decimation filters allow for the creation of the following (Gen 1/Gen 2):
- All filter stages are bypassed
- Decimation filtering using a single stage
- Decimation filtering using two stages
- Decimation filtering using all three available stages
Each decimation filter element has a different number of taps and the stop-band attenuation and ripple are shown in Decimation Filter Details. The decimation filter chains can operate on either I/Q data or real data. Unused filter chains are powered down.
Each of the filter stages can overflow given the step-response of a FIR filter, especially when full-scale data is on the input. To detect and protect the datapath from overflow, each filter stage and sub-phase has a signed overflow status signal and saturation at the output. When a filter stage is not used, the flag is forced zero. These flags are connected to the datapath interrupt mechanism which is described in Interrupt Handling. The multiplexer in the following figure shows the decimation level selected in the IP configuration with the corresponding selection of decimation filter blocks.
|Quad and Dual RF-ADC Tile|
|OFF||The entire filter is disabled/powered down (applies when RF-ADC is disabled)|
|1x||The entire filter is bypassed|
|2x||2x decimation, 80% Nyquist passband 1|
|4x||4x decimation, 80% Nyquist passband|
|8x||8x decimation, 80% Nyquist passband|