RF-ADC Digital Datapath - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

An RF-ADC component in a tile has integrated DSP features which you can enable to pre-process the sampled data from the RF-ADC device before it is passed to the PL. The different DSP function blocks are as follows:

Detection functionality
Contains a dual level programmable threshold that provides two flags to the internal interconnect logic, and is asserted when the absolute output value of the RF-ADC is greater or smaller than the programmed threshold values.
Compensation functionality
Contains a quadrature modulator correction (QMC) block with a coarse delay adjustment block
Digital Down Converter (DDC)
consists of
  • Mixer—coarse (quarter and half rate) and fine (NCO with 48-bit frequency resolution)
  • Gen 1/Gen 2: Signal decimation functionality—decimation by 1 (bypass), 2, 4, or 8 is supported.
  • Gen 3/DFE: Signal decimation functionality—decimation by 1 (bypass), 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 40 is supported.

Single, multiple, or all DSP functions can be used or bypassed. Some functions, such as the QMC, require activation of the same function in both I and Q RF-ADCs. Even numbered RF-ADCs are always used for I datapaths, and odd numbered RF-ADCs are used for Q datapaths. You can implement, configure, or modify the functionality of one or multiple functions using the IP core. The following figure shows the available functions in an RF-ADC and the functions are described in this section.

Figure 1. Signal Treatment of the RF-ADC Peripherals