RF-ADC Programmable Logic Data Interface - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

The data interface between the RF-ADC tiles and the PL is implemented using parallel data streams, using the AXI4-Stream protocol. These data streams are output through the gearbox FIFOs which provide a flexible interface between the user application and the RF-ADC tile. The maximum interface width is 128 bits per stream, representing up to eight 16-bit little endian words. For Gen 3/DFE, the maximum interface width is 192 bits, representing up to 12 16-bit little endian words. The data streams and associated FIFOs have a configurable number of words which provide the flexibility to choose between the number of words and clock frequency to interface with the PL design. There are four streams per tile, and the naming convention is mXY_axis, where X represents the RF-ADC tile number and Y represents a stream (FIFO) output from that tile. The following figure shows the interfaces.

Figure 1. Dual RF-ADC Tile Programmable Logic Data Interface