RF-DAC Features - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English
  • Tile configuration
    • Gen 1/Gen 2: Four RF-DACs and one PLL per tile
    • Gen 3/DFE: Four or two RF-DACs and one PLL per tile
    • 14-bit RF-DAC resolution with 16-bit digital signal processing path; the data is MSB-aligned to 16 bits
    • Device-dependent sampling speed; see the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889)
  • Interpolation
    • Gen 1/Gen 2: 1x (bypass filter), 2x, 4x, 8x
    • Gen 3/DFE: 1x (bypass filter), 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x, 40x; an additional 2x is available in IMR mode
    • 80% pass band, 89 dB stop band attenuation
  • Digital Complex Mixers
    • Full complex mixers support real or I/Q output signals to the RF-DACs
    • 48-bit NCO per RF-DAC
    • Fixed Fs/4, Fs/2 low-power frequency mixing mode
    • Supports mixed mode RF-DAC functionality which maximizes RF-DAC power in the second Nyquist zone
  • Single/multi-band flexibility
    • 2x bands per RF-DAC pair
    • 4x bands per RF-DAC tile
    • Can be configured for real or I/Q outputs
  • Full Nyquist bandwidth in bypass mode
  • Digital Correction for external analog quadrature modulators:
    • Supports gain, phase, and offset correction for an I/Q output pair (two RF-DACs)
  • Gen 1/Gen 2: Sinc correction for first Nyquist zone
  • Gen 3/DFE: Sinc correction for first and second Nyquist zones
  • External input signal (SYSREF) for multi-channel synchronization of data converter channels
  • Per tile current mode logic (CML) clock input buffer with on-chip calibrated 100Ω termination; supplies the RF-DAC sampling clocks or provides a reference clock for the on-chip PLL (does not apply to odd numbered Dual RF-DAC-only tiles)
  • Gen 1/Gen 2: Supports 20 mA or 32 mA output power mode
  • Gen 3/DFE: Variable Output Power (VOP) supports full-scale current sink, backward compatible 20/32 mA mode for Gen 1 and Gen 2
  • Gen 3/DFE: Power saving mode of individual function blocks in Time Division Duplexing (TDD) application

For the RF-ADC and RF-DAC operating and absolute maximum/minimum parameters see:

  • Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889)
  • Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)