RF-DAC/RF-ADC Tile <n> FIFO Disable Register (0x0230) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2023-10-18
Version
2.6 English
Table 1. RF-DAC/RF-ADC Tile <n> FIFO Disable Register (0x0230)
Bit Default Value Access Type Description 1,2
31:1 - - Reserved
0 0 R/W Disable the interface FIFO for converter <n>
  1. <n> is 0 to 3.
  2. See Register Space for register <n> address.