Real-Time NCO Signal Interface Ports for RF-DACs - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2023-10-18
Version
2.6 English
Table 1. Real Time NCO Signal Interface Ports for RF-DACs
Port Name 1 I/O Clock Description
dacXY_nco_freq[47:0] In s_axi_aclk Requested NCO frequency setting. This is a 48 bit signed input representing the NCO frequency. The value ranges from -Fs/2 to Fs/2, where Fs is the sampling rate.
dacXY_nco_phase[17:0] In s_axi_aclk Requested NCO Phase setting. This is a 18 bit signed number representing the NCO phase. The value ranges from -180 to 180 degrees.
dacXY_nco_phase_rst In s_axi_aclk NCO phase reset. Used to align the NCO phases across the converter.
dacXY_nco_update_en[5:0] In s_axi_aclk Enable register writes
  • Bit 5: Enable write to phase reset
  • Bit 4: Enable write to NCO phase bits 17:16
  • Bit 3: Enable write to NCO phase bits 15:0
  • Bit 2: Enable write to NCO frequency bits 47:32
  • Bit 1: Enable write to NCO frequency bits 31:16
  • Bit 0: Enable write to NCO frequency bits 15:0
dacX_nco_update_req In s_axi_aclk Asserted High to request an update of the NCO settings.
dacX_nco_update_busy[1:0] Out s_axi_aclk Update busy register
  • Bit 1: High while SYSREF is disabled. Applicable for RF-DAC tile 0 when multi-tile synchronization has been selected
  • Bit 0: High when the NCO update is in progress.
dac0_sysref_int_gating In s_axi_aclk Applicable for RF-DAC tile 0 when multi-tile synchronization is enabled. When asserted the disabling of the SYSREF is carried out by the IP core.
dac0_sysref_int_reenable In s_axi_aclk Applicable for RF-DAC tile 0 when multi-tile synchronization is enabled. When asserted the IP core re-enables the SYSREF after the NCO update process has completed. In multi-device systems all devices should be re-enabled at the same time.
  1. X refers to the location of the tile in the converter column. Y refers to the location of the DUC block in the tile (0 to 3).