Real-Time TDD Signal Interface for Quad RF-ADCs (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English
Table 1. Real-Time TDD Signals for Quad RF-ADCs
Port Name 1 I/O Clock Description
adcXY_tdd_mode In s_axi_aclk Time Division Duplexing control signal. A logic high on this input will power down the channel.
  1. X refers to the location of the tile in the converter column. Y refers to the location of the DDC block in the tile (0 to 3).