Restart Tile - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2023-10-18
Version
2.6 English

To restart a tile and perform the complete power-on sequence after initialization under software control, perform the following steps:

  1. Either
    1. Write 0x0000_000F to the tile<n> Restart State register to restart with the Vivado IDE configuration or
    2. Write 0x0000_010F to the tile<n> Restart State register to restart with the current configuration (which might be different from the Vivado settings).
  2. Write 0x0000_0001 to the tile<n> Restart Power-On State Machine register to restart the tile.
  3. Poll the tile<n> Restart Power-On State Machine register to check operation is complete; the power-on sequence is complete when this register reads all zeros.