SYSREF signal is the timing reference for the system
and must therefore be handled correctly to ensure it does not degrade the
synchronization. This signal has the following requirements.
SYSREFmust be a high-quality, free-running, low-jitter signal, to allow it to be captured consistently by the analog sample clock. See the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) for the
SYSREFfrequency must meet the following requirements:
- If synchronizing RF-ADC and
RF-DAC tiles with different sample
frequencies, the frequency must be an integer submultiple of:
SYSREFmust also be an integer submultiple of all PL clocks that sample it. This is to ensure the periodic
SYSREFis always sampled synchronously.
- Less than 10 MHz.
- If synchronizing RF-ADC and RF-DAC tiles with different sample frequencies, the frequency must be an integer submultiple of:
SYSREFmust be safely captured by the PL, before passing to the core:
- Setup/hold of
PL_clockmust be handled as part of the user design.
- Clock generation on the PCB can be used to facilitate this, if supported.
- Setup/hold of
SYSREFmust be the same frequency and have a constant phase relationship. If deterministic latency is required, the analog
SYSREFmust keep the same phase difference over reset to reset cycles.
- For MTS synchronization, which covers both divider phase sync and
FIFO latency sync, the analog
SYSREFmust be a continuous clock for the duration of the MTS procedure. It can be either AC-coupled or DC-coupled. The
SYSREFsignals can be shut down after the completion of the MTS procedure.Note: The signals should be turned on and stabilized prior to the MTS function call.
- If analog
SYSREFis being used to synchronize the phase of the DUC/DDC mixer NCOs across multiple Zynq® UltraScale+™ RFSoCs, then it must be DC-coupled with the ability to generate single or multiple pulse waveforms.