Single Converter Mode - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2022-10-21
Version
2.6 English

When multi-tile synchronization (MTS) is not supported all the converters are independent. An NCO update state machine is instantiated for each converter. Before a NCO update can be performed the event source must be set to Tile. See Dynamic Update Events for more information on setting the event source.

The process for updating the NCO settings is shown below.

Figure 1. Single Converter NCO Update
  1. Firstly the required frequency, phase, and phase reset values are set on the real-time NCO signal interface ports.
  2. The update enable port is set to indicate which converter register values are to be updated. The more values that are required to be updated increases T1 (the time to write the NCO values into the converter registers). In the RF-DAC and Quad RF-ADC cases writing one register typically takes 29 s_axi_aclk cycles. Each additional register write increases T1 by three s_axi_aclk cycles.

    In the Dual RF-ADC case, writing one register typically takes 45 s_axi_aclk cycles. Each additional register write increases T1 by six s_axi_aclk cycles.

  3. A pulse is then sent to the update request port. If the IP state machine has completed the start up process the access to the requested NCO registers commences.
  4. The busy signal remains High until the NCO update process is complete. The frequency, phase, and phase reset values should be held until the busy signal is deasserted.