In the TDD power saving mode, each converter channel is independently controlled using the PL inputs. The tile synchronization, clocking, and channel states are preserved. The interleaving calibration is automatically handled without user intervention when an RF-ADC is put in power down and wake up states.
The following diagram illustrates TDD power saving mode.
A real time tdd_mode signal is available
to enter and exit power saving mode for each converter. During power down state, both
RF-ADC and RF-DAC
output 0.
When multiple converter channels are present, the Zynq UltraScale+ RFSoC RF Data Converter IP core uses a small internal delay to stagger the start-up of channels to prevent a large step-in current on the supplies.
For more details on designing Power Distribution Networks when using the TDD power saving mode, see the UltraScale Architecture PCB Design User Guide (UG583).
For an example of how to control the TDD mode pins, see the Zynq UltraScale+ RFSoC ZCU208 and ZCU216 RF Data Converter Evaluation Tool User Guide (UG1433).