Test Bench - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

This chapter contains information about the test bench provided in the Vivado® Design Suite.

For information on setting up and running simulations in the Vivado Design Suite, see the Vivado Design Suite User Guide: Logic Simulation (UG900). Zynq® UltraScale+™ RFSoC RF Data Converter core supports behavioral simulation along with post-implementation functional simulation.

The following figure shows the structure of the Zynq® UltraScale+™ RFSoC RF Data Converter test bench.

Figure 1. Demonstration Test Bench
The following blocks are present in the demonstration test bench.
Clock Generator
This block produces the required AXI4-Lite and AXI4-Stream clocks for the design.
DAC Source
This block outputs a series of samples representing a tone at a set frequency. These samples are written in to the data stimulus block in the example design.
DAC Sink
This block performs a FFT on the RF-DAC analog output. It checks that the input tone appears at the expected frequency.
ADC Source
The RF-ADC analog inputs are driven by a tone at a set frequency. If the mixers in the RF-ADC are enabled the tone is mixed with a sine wave before being input to the RF-ADC . The mixer in the ADC source block is set to run at the negative of the mixer frequency in the converter.
ADC Sink
This block performs a FFT on the RF-ADC digital output. It checks that the input tone appears at the expected frequency.
This block is responsible for managing accesses to the test bench components through an AXI4-Lite interface. It contains examples of how to access and configure the basic test harness.
The sequencer in the demonstration test bench runs through the following stages. At some stages the Power-up sequence state machine is stopped despite the sequence not being complete. This is in order to speed up the simulation. It is not essential to follow the steps in the demonstration test bench for simulation of the converters. The state machine can be allowed to run from start to finish without being restarted.
  1. The test bench components are set up. The sources and sinks are set up with the configuration information from the IP core. The power-up sequence state machine is started and the initial configuration stage is completed.
  2. Sine waves from the DAC Source block are written into the memory in the stimulus block for each enabled channel.
  3. Some of the configuration registers are then changed to help speed up the simulation. For example, in the RF-ADC the dither is disabled. This allows the calibration step in the power-up sequence to be skipped, saving simulation time. When the fine mixers are enabled they can also be reprogrammed at this point to minimize any spectral leakage in the FFT.
  4. The RF-DACs and RF-ADCs are then run to the stage before the converter clocks are released to the digital section of the converters. The simulation is slowed when the converter clocks are enabled and stopping the state machine at this stage helps to reduce run time.
  5. The RF-DACs are fully powered up and the transmission of data from the stimulus block is started.
  6. The sequencer waits for the DAC Sink blocks for each RF-DAC output to report their FFT results. The RF-DACs are then powered down.
  7. The RF-ADCs are powered up to the start of the foreground calibration stage and data capture is started for each of the enabled channels.
  8. When data capture is complete the RF-ADCs are powered down. The sequencer then reads the captured data back and sends it to the ADC Sink block.
  9. The sequencer waits for the ADC Sink blocks for each enabled channel to report their FFT results. The simulation then completes.

When Fs/2 mixing is enabled output similar to that in the following figures should be visible on the analog I/O.

Figure 2. RF-ADC Analog I/O
Figure 3. RF-DAC Analog I/O