Tile Clock Settings - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2023-10-18
Version
2.6 English

The sampling rate and clock frequencies are set in this section.These settings are shared by each converter in a tile.

Sampling Rate (GSPS)
Sets the sampling rate for each tile. It is configurable when at least one of the converters in the tile is enabled. Valid values depend on the selected device and package. These values can be found in Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
Max Fs (GSPS)
The maximum sample rate for each tile is given for reference.
PLL
Selects whether the PLL within the tile is being used or bypassed. It is configurable when at least one of the converters in the tile is enabled. If it is required to dynamically reconfigure the PLL using the RFdc driver API, the PLL must be enabled in the Vivado IDE. Valid values are True or False.
Reference Clock (MHz)
Sets the frequency of the clock input for the tile. It is configurable when the PLL and at least one of the converters in the tile is enabled. Its values depend on the sampling rate of the tile. A drop-down list of values based on the sample rate selected is presented. It is recommended to use the correct reference frequency at the PLL input for optimum phase noise performance. See the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) for the FREF specification.
PLL Reference Clock
Sets the frequency of the PLL input clock if the PLL is enabled for a specific tile.
Reference Clock Divider
Sets the divider on the PLL reference clock input.
Fabric Clock (MHz)
This is the frequency of the clock to be supplied on the AXI4-Stream clock input for the selected tile. The required frequency is determined by the sample rate and the settings in the Converter Configuration. Because all AXI4-Stream ports on a tile share a common AXI4-Stream clock all converter configurations on a tile must require the same clock frequency.
Clock Out (MHz)
Sets the frequency of the output clock on the tile. This clock can be used to drive the AXI4-Stream clock inputs. It is configurable when at least one of the converters in the tile is enabled. The values depend on the sampling rate of the tile. A drop-down list of values based on the sample rate selected is presented.
Clock Source (Gen 3/DFE)
Sets the clock source for each tile. For Gen 3 devices with only Dual RF-DACs, the clock source for each enabled RF-DAC must be set to an even numbered tile.
Distribute Clock (Gen 3/DFE)
Sets whether the tile will distribute a clock to other tiles on the device.
Off
No clock is forwarded from the tile.
Input Refclk
When the PLL is enabled the input reference clock is forwarded from the tile. If the PLL is not enabled then the input sampling clock is distributed.
PLL Output
When the PLL is enabled the clock output from the PLL is forwarded from the tile.