User Interface - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2023-10-18
Version
2.6 English
The RF Analyzer IP integrator design can be integrated into user designs. Access to the RF-DAC AXI4-Stream interface is provided through the following ports.
Table 1. RF-DAC User Interface
Port Name 1 I/O Clock Description
sX_axis_aclk Out N/A AXI4-Stream clock output from the MMCM in the clocking block
sXY_0_tdata In sX_axis_aclk AXI4-Stream data input
sXY_0_tvalid In sX_axis_aclk AXI4-Stream valid
sXY_0_tready Out sX_axis_aclk AXI4-Stream ready
user_select_XY_0 In sX_axis_aclk When this input is driven High the RF-DAC is driven from the user interface. When Low the RF-DAC is driven by the data stimulus block in the RF Analyzer.
  1. X refers to the location of the tile in the converter column. Y refers to the location of the DUC block in the tile (0 to 3).
The AXI4-Stream interface is routed out to the user design through the ports described in the following table.
Table 2. RF-ADC User Interface
Port Name 1 I/O Clock Description
mX_axis_aclk Out N/A AXI4-Stream clock output from the MMCM in the clocking block
mXY_0_tdata Out mX_axis_aclk AXI4-Stream data output
mXY_0_tvalid Out mX_axis_aclk AXI4-Stream valid
mXY_0_tready In mX_axis_aclk AXI4-Stream ready. Tie Low when the user interface is not in use. The RF Analyzer data capture block should be disabled when the user interface is in use.
  1. X refers to the location of the tile in the converter column. Y refers to the location of the DUC block in the tile (0 to 3).