XRFdc_DynamicPLLConfig - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2023-10-18
Version
2.6 English

Function Prototype

u32 XRFdc_DynamicPLLConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 Source, double RefClkFreq, double SamplingRate);

Arguments

XRFdc *InstancePtr
Pointer to the driver instance.
u32 Type
RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC.
u32 Tile_Id
RF-ADC/RF-DAC tile number. Valid values are 0-3.
u8 Source
Internal PLL or external clock source.
Table 1. Valid Macros for Source Argument
Macro Description
XRFDC_EXTERNAL_CLK For external clock
XRFDC_INTERNAL_PLL_CLK For internal PLL
double RefClkFreq
Reference clock frequency in MHz (FREF min to FREF max).
double SamplingRate
Sampling rate frequency in MHz (Fs min to Fs max).
Important: For the FREF and Fs specifications see the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).

Description

This API function is used for dynamic switching between the internal PLL and the external clock sources, and for configuring the internal PLL for the RF-ADCs/RF-DACs.

Return Value

XRFDC_SUCCESS

XRFDC_FAILURE