XRFdc_SetDecimationFactor - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2023-10-18
Version
2.6 English

Function Prototype

u32 XRFdc_SetDecimationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 DecimationFactor);

Arguments

XRFdc *InstancePtr
Pointer to the driver instance.
u32 Tile_Id
RF-ADC tile number. Valid values are 0-3.
u32 Block_Id
RF-ADC number. Valid values are 0-3.
u32 DecimationFactor
Decimation factor to be set for the RF-ADC.
Table 1. Valid Macros for DecimationFactor Argument
Macro Description
XRFDC_INTERP_DECIM_OFF Decimation is OFF
XRFDC_INTERP_DECIM_1X 1X Decimation factor
XRFDC_INTERP_DECIM_2X 2X Decimation factor
XRFDC_INTERP_DECIM_3X 3X Decimation factor 1
XRFDC_INTERP_DECIM_4X 4X Decimation factor
XRFDC_INTERP_DECIM_5X 5X Decimation factor 1
XRFDC_INTERP_DECIM_6X 6X Decimation factor 1
XRFDC_INTERP_DECIM_8X 8X Decimation factor
XRFDC_INTERP_DECIM_10X 10X Decimation factor 1
XRFDC_INTERP_DECIM_12X 12X Decimation factor 1
XRFDC_INTERP_DECIM_16X 16X Decimation factor 1
XRFDC_INTERP_DECIM_20X 20X Decimation factor 1
XRFDC_INTERP_DECIM_24X 24X Decimation factor 1
XRFDC_INTERP_DECIM_40X 40X Decimation factor 1
  1. Gen 3/DFE only.

Description

This API function sets the decimation factor for the requested RF-ADC and also updates the FIFO write width based on the decimation factor.

Dynamic change in decimation has an impact on the block throughput. The AXI4-Stream clock rate can be dynamically changed to account for this change of throughput. In non-MTS mode, the recommended procedure is to turn off the FIFO (Xrfdc_setupfifo), change the clock rate (Xrfdc_SetfabClkOutDiv), clear the FIFO interrupt, and restart the FIFO (Xrfdc_SetupFifo).
Note: This function is only applicable for RF-ADCs.

Return Value

XRFDC_SUCCESS

XRFDC_FAILURE