XRFdc_SetFabClkOutDiv - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2023-10-18
Version
2.6 English

Function Prototype

u32 XRFdc_SetFabClkOutDiv(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u16 FabClkDiv);

Arguments

XRFdc *InstancePtr
Pointer to the driver instance.
u32 Type
RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC.
u32 Tile_Id
RF-ADC/RF-DAC tile number. Valid values are 0-3.
u16 FabClkDiv
PL clock divider to be set for a tile.
Table 1. Valid Macros for FabClkDiv Argument
Macro Description
XRFDC_FAB_CLK_DIV1 Divided by 1
XRFDC_FAB_CLK_DIV2 Divided by 2
XRFDC_FAB_CLK_DIV4 Divided by 4
XRFDC_FAB_CLK_DIV8 Divided by 8
XRFDC_FAB_CLK_DIV16 Divided by 16

Description

Use this function to set the divider for PL clock out.
Note: This is a common function for RF-ADCs and RF-DACs.

Return Value

XRFDC_SUCCESS

XRFDC_FAILURE