This structure contains the clock distribution status/information parameters.
u8 MaxDelay;
u8 MinDelay;
u8 IsDelayBalanced;
u8 Source;
u8 UpperBound;
u8 LowerBound;
XRFdc_Tile_Clock_Settings ClkSettings[2][4];
Description
- u8 MaxDelay
- This is the maximum delay from the source tile to the farthest tile in the distribution.
- u8 MinDelay
- This is the minimum delay from the source tile to the farthest tile in the distribution.
- u8 IsDelayBalanced
- This indicates whether or not the distribution is delay balanced. The values are 0 (not balanced) and 1 (balanced).
- u8 Source
- The distribution source tile using the package id indexing.
- u8 UpperBound
- This is the tile at the edge of the distribution on the side closest to ADC 0. This is package id indexed.
- u8 LowerBound
- This is the tile at the edge of the distribution on the side closest to DAC 3. This is package id indexed.
- XRFdc_Tile_Clock_Settings ClkSettings[2][4]
- A structure which contains information about a given tile in the distribution, the array is indexed as [Type][TileId]. This does not need to be populated to set the clock distribution.
Macro | Description |
---|---|
XRFDC_CLK_DST_TILE_224 | ADC Tile 0 |
XRFDC_CLK_DST_TILE_225 | ADC Tile 1 |
XRFDC_CLK_DST_TILE_226 | ADC Tile 2 |
XRFDC_CLK_DST_TILE_227 | ADC Tile 3 |
XRFDC_CLK_DST_TILE_228 | DAC Tile 0 |
XRFDC_CLK_DST_TILE_229 | DAC Tile 1 |
XRFDC_CLK_DST_TILE_230 | DAC Tile 2 |
XRFDC_CLK_DST_TILE_231 | DAC Tile 3 |