struct XRFdc_Signal_Detector_Settings (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2023-10-18
Version
2.6 English

This structure is used to set or get the signal detector settings.

u8 Mode;
	u8 TimeConstant;
	u8 Flush;
	u8 EnableIntegrator;
	u16 Threshold;
	u16 ThreshOnTriggerCnt;
	u16 ThreshOffTriggerCnt;
	u8 HysteresisEnable;

Description

u8 Mode
Whether to use Average or Randomized mode.
u8 Flush
Flush the leaky integrator.
u8 TimeConstant
Time constant of the leaky integrator.
u8 EnableIntegrator
Enable the leaky integrator.
u16 Threshold
The threshold for signal detection.
u16 ThresholdOnTriggerCnt
The number of times value must exceed Threshold before turning on.
u16 ThresholdOffTriggerCnt
The number of times value must exceed Threshold before turning off.
u8 HysteresisEnable
Enable hysteresis on signal on.
Table 1. Valid Macros for Mode
Macro Description
XRFDC_SIGDET_MODE_AVG Average mode of operation
XRFDC_SIGDET_MODE_RNDM Randomized mode of operation
Table 2. Valid Macros for TimeConstant
Macro Description
XRFDC_SIGDET_TC_2_0 2^0 Cycles
XRFDC_SIGDET_TC_2_2 2^2 Cycles
XRFDC_SIGDET_TC_2_4 2^4 Cycles
XRFDC_SIGDET_TC_2_8 2^8 Cycles
XRFDC_SIGDET_TC_2_12 2^12 Cycles
XRFDC_SIGDET_TC_2_14 2^14 Cycles
XRFDC_SIGDET_TC_2_16 2^16 Cycles
XRFDC_SIGDET_TC_2_18 2^18 Cycles