AXI Considerations - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

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1.0 English

The HBM IP requires a fixed AxSIZE of 0x5 for 32 bytes (256 bits) and it is recommended to have a minimum AxLEN of 0x1 to gain higher performance for linear accesses. Undersized AXI writes are supported by using the WSTRB port but these accesses decrease the total system performance. This is because the same amount of HBM protocol execution and interface time is used to service a full 32-byte Write as is used for an 8-byte Write. With this example the effective peak bandwidth is only 25% of the theoretical maximum.

Another AXI consideration is to make sure that the AXI Write and Read addresses are aligned to the HBM physical address space and transaction size. The lower five bits of the AWADDAR and ARADDR should be unused to ensure that accesses align to the 32-byte HBM burst boundary. This is because each individual Write or Read transaction on the HBM interface is a burst length of 4 with a DQ bus width of 64 bits, resulting in a total of 32 bytes. The AXI address space is a byte address, so 32 bytes result in 5 bits of addressing, and these are placed at the bottom of the address space. If an AXI transaction has a non-zero value in these lower address bits, the HBM controller must execute multiple commands on the HBM interface. In the case of an unaligned Read operation, two Reads are required on the HBM interface to gather the data. The controller then coalesces this to the expected payload which is delivered to the AXI Read channel. Here, the effective bandwidth is 50% or less depending on the additional protocol churn on the HBM interface. The same situation can occur with an unaligned Write, where a single Write request executes as two writes on the HBM interface while using the data mask pins to mask the unused portion of the Write payload. If ECC is enabled, an unaligned Write executes as two Read/Modify/Write (RMW) operations. When ECC is enabled the HBM controller cannot use the Data Mask pins so the first portion of the unaligned Write needs to be Read from the memory, then modified by the controller for a new data payload, and finally written back to the HBM. This process is executed twice because it requires two RMW operations to service the unaligned Write along the HBM burst boundaries.

The last AXI consideration is that the Write and Read channels operate independently while there is only a single electrical interface on the HBM stacks. This means that the HBM controller only executes Write operations and then must wait for the appropriate period of protocol time to service a bus turnaround before it can issue Read operations. For the highest possible efficiency, the user logic should minimize bus turnarounds, maximize the amount of time spent moving data in one direction before having to go the other way, or at least have a highly deterministic access pattern that minimizes protocol churn for simultaneous Write and Read streams.