There are three clock types that must be provided to the HBM core:
- The
HBM_REF_CLK_x
drives a PLL which then generates a clock for the eight memory controllers, as well as the memory clock for the HBM stack. There is one PLL per HBM stack. This clock must be sourced from a MMCM/BUFG, or from a BUFG. TheHBM_REF_CLK_x
can be sourced from the cascading clocking sources derived from another clock. The source clock for this derived clock must come from aGCIO
pin within the same SLR as the HBM. The clock generator driving the GCIO should have jitter less than 3 pS RMS. - The
APB_x_PCLK
is used for the APB register port access. This can be asynchronous to the other clocks. There is one APB clock port per HBM stack. TheAPB_x_PCLK
can be sourced from the cascading clocking source orMMCM
orGCIO
pin. - The
AXI_xx_ACLK
is the clock for each of the AXI ports. These can be asynchronous to the other clocks. TheAXI_xx_ACLK
can be sourced from the cascading clocking source orMMCM
orGCIO
pins.
The global routing switch does not have a separate clock input, but rather
shares one of the AXI_xx_ACLKs
. This is automatically selected by the
software to be one of the clocks in the middle of the user-selected memory controllers. This
can be checked by looking at the hbm_0.v file. There are
parameters, CLK_SEL_xx
, and only one has the attribute TRUE.
For maximum efficiency, it is important that the AXI clock selected is the highest frequency of all of the AXI port clocks.