The AXI High Bandwidth Memory Controller provides access to one or both the 1024-bit wide HBM stacks depending on the selected device; 64 Gb for 4H devices or 128 Gb for 8H devices. Each stack is split into eight independent memory channels, each of which is further divided into two 64-bit pseudo channels. Pseudo channel memory access is limited to its own section of the memory (1/16 of the stack capacity). Furthermore, each memory channel can operate at an independent clock rate that is an integer divide of a global reference clock.
The AXI HBM Controller has simplified the interface between HBM and CLB-based user logic in several ways. The AXI3 protocol is selected to provide a proven standardized interface. The 16 AXI ports provided match the total throughput of the HBM. Each port operates at a 4:1 ratio to lower the clock rate required in the user logic. This ratio requires a port width of 256-bits (4 × 64). Each AXI3 channel has 6-bit AXI ID port which helps in reordering transactions to achieve the required bandwidth. On the selected AXI3 channel, if the transactions are triggered using a different ID tag, then the transactions are reordered as per the AXI3 protocol. Conversely, if the selected AXI3 channel transactions are triggered using same ID tag, then the transactions are executed sequentially in the order they are triggered.
The ports are distributed across the general interconnect to reduce congestion and each port is based on an independent clock domain. This flexibility, along with each AXI port attached to its own registered column interface, reduces congestion and eases timing closure.
The 16 × 16 AXI crossbar switch is included in this core which allows each memory port to access the full HBM space by addressing all 16 pseudo channels. In the case of a two-stack system, this is extended to a 32 × 32 crossbar to allow direct access across both HBM stacks as shown in the following 4H device figure.
