Figure 1. Data Path Error Protection Scheme
- BRESP error
- Occurs if host parity is enabled and a parity error is detected in the AXI port for any of the associated AXI Write data. An error drives 2'b10 on the BRESP port.
- RRESP error
- Occurs if the corresponding read data has either a parity error or an
uncorrectable ECC error. The parity error check covers the path from HBM
memory to AXI RDATA output port. An error drives 2'b10 on the RRESP
port.Note: If parity retry is enabled, the error response will be asserted only if there is no read data transfer without parity errors.
- DERR signal pulse
- Occurs if the HBM detects a parity error on Write data received. The
DERRsignal does not indicate exactly which AXI Write data command has caused the parity error. - WDATA error insertion
- Occurs if a Write data parity error is detected within the memory controller pipeline. Write data is corrupted to ensure that an ECC error will be detected at a later point when the data is read.