Example Design - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

Document ID
PG276
Release Date
2021-08-06
Version
1.0 English

This chapter contains information about the example design provided in the Vivado® Design Suite.

This following section contains steps for running the HBM controller simulations using the Vivado® HBM Example Design. Simulation is supported with the Verilog Compiler Simulator (VCS), Incisive Enterprise Simulator (IES), and Mentor Graphics Questa Advanced Simulator. For a list of known issues, see AR 69267 for the AXI HBM Controller.